This is an advanced, research-oriented and project-based course with extensive hands-on experience.
Increasing design complexity and advances in semiconductor technology provide the opportunity to have all parts of a digital system as a System on a Chip (SOC), where parts of system functionality are developed as software and parts as hardware following Hardware/Software partitioning paradigm. Also, it is necessary to be able to design, re-use and exchange Intellectual Property (IP) (both hardware and software) in a systematic, reliable and easy way. Therefore, advanced methodologies and tools are needed on a system-level for digital system design, validation and verification at different levels of abstraction. System-level design can help cope with the growing complexity of both the hardware and software. While software design is based on the use of high-level programming languages with design cycle that allows relatively easy and quick modifications and revisions, hardware design deals with much lower level of abstraction and requires specific design expertise, including the knowledge of the architecture on which hardware will be mapped and implemented. This results in achieving shorter time to market for systems in addition to providing better opportunities for quality system design and verification.
As most of the designs require final synthesizable design representation, hardware description languages, such as VHDL and Verilog, are most often used for the final design. A refresher of VHDL and register-transfer level design will be made in this course and then the language will be used to target relatively complex designs, such as complete processor or heterogeneous multi-core SoC, on one hand, or behaviourally specified algorithms, on the other hand. Both these directions of digital systems design will be further analysed and their use in real designs demonstrated. This includes using FPGAs as the target implementation technology that allows the development of specialised reconfigurable chips. Also, aspects of the synthesis from the high level specifications (High-Level Synthesis, HLS) using programming language inputs and their synthesis into hardware accelerators or application-specific processors will be discussed.
The course is completely assessed by the coursework. Assessment of the work on project is through a number of checkpoints and final report and presentation in the class.